Milpitas, CA 95035


The candidate will work with the designers to integrate the design from floorplan to production quality GDSII. The Candidate needs to understand the complexity of integrating various IP’s and IO pad ring generation in floorplan. A candidate will work with the DFT, Packaging and fellow PnR resources to close on various aspect of floorplan, placement, clock tree generation, ECO, timing convergence, LVS/DRC, etc.

Responsibilities include:

Generate/Optimize pad ring and core by working with cross-functional teams including front-end designers, package designer, and System board design team. A candidate will design the floorplan by integrating the gate-level netlist and timing constraints. Estimate/Optimize chip/die size. Work with engineers to identify IO ring and IO voltage domains. Support synthesis teams with feedback from the Place and Route perspective and integration.

Key Qualifications

Demonstrate successful results for multiple ASIC programs, is required.

You will need to be very organized with solid understanding of Cadence design tools and flows. You need to have solid experience as below:

  • Direct hands-on experience on complex SOC tapeout
  • Hands on experience with Cadence EDA tools.
  • Integration of various IP’s including: PHY, PLL, etc
  • Ability to work with cross-functional teams to troubleshoot floorplan, timing, power and packaging issues.
  • Familiarity with deep sub-micron design rules


MS + 10 years industrial experience

BS + 12 years industrial experience

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